A node or pin in a system is a fail-safe pin when it is possible for the voltage at the pin to be greater than VDD, a condition that should be protected against. To manage this problem, a fail-safe circuit generates a fail-safe signal to prevent the flow of current towards VDD. When a fail-safe pin is shared by multiple circuit blocks, undesired interactions can occur in certain situations. Applicants have noted that a circuit block that is in power-down mode can still affect settling time in other blocks sharing the same fail-safe pin. It is desirable that a block in power-down mode have no effect on blocks that share a fail-safe pin.